Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry

ABSTRACT

Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.

TECHNICAL FIELD

This invention relates to semiconductor processing methods of formingintegrated circuitry and to semiconductor processing methods of formingdynamic random access memory (DRAM) circuitry.

BACKGROUND OF THE INVENTION

Processing of semiconductor devices typically involves many steps whichinclude masking, doping, and etching. Each time one of these steps isperformed, certain risks can arise which can jeopardize the integrity ofa wafer being processed. For example, a mask misalignment error cancause a subsequent etch to undesirably etch into wafer or substratestructure which can cause catastrophic failure. Accordingly, it isdesirable to reduce the number of processing steps utilized in theformation of integrated circuitry.

This invention arose out of concerns associated with reducing the numberof processing steps needed in the formation of integrated circuitry.This invention also arose out of concerns associated with improving themanner in which integrated circuitry memory devices, and in particulardynamic random access memory (DRAM) devices are fabricated.

SUMMARY OF THE INVENTION

Semiconductor processing methods of forming integrated circuitry, and inparticular, dynamic random access memory (DRAM) circuitry are described.In one embodiment, a single masking step is utilized to form maskopenings over a substrate, and both impurities are provided and materialof the substrate is etched through the openings. In one implementation,openings are contemporaneously formed in a photo masking layer oversubstrate areas where impurities are to be provided, and other areaswhere etching is to take place. In separate steps, the substrate isdoped with impurities, and material of the substrate is etched throughthe mask openings. In another implementation, two conductive lines areformed over a substrate and a masking layer is formed over theconductive lines. Openings are formed in the masking layer in the samestep, with one of the openings being received over one conductive line,and another of the openings being received over the other conductiveline. Impurities provided through an opening into the substrateproximate one conductive line, and material from over the otherconductive line is removed through the other opening to at leastpartially form a contact opening over the other conductive line.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a semiconductor wafer inprocess, in accordance with one aspect of the invention.

FIG. 2 is a view of the FIG. 1 wafer at a different processing step.

FIG. 3 is a view of the FIG. 2 wafer at a different processing step.

FIG. 4 is a view of the FIG. 3 wafer at a different processing step.

FIG. 5 is a diagrammatic sectional view of a semiconductor waferfragment undergoing processing, in accordance with a preferredembodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

Referring to FIG. 1, a semiconductor wafer fragment in process is showngenerally at 10 and includes a semiconductive substrate 12. In thecontext of this document, the term “semiconductive substrate” is definedto mean any construction comprising semiconductive material, including,but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above. Preferably, substrate 12comprises a bulk monocrystalline substrate.

In the illustrated example, substrate 12 includes a pair of field oxideregions 14 with a thin oxide layer 16, e.g., around 60 Angstroms,extending therebetween. A pair of conductive lines 18, 20 are formedover substrate 12. The two illustrated conductive lines include apolysilicon layer 22 and a silicide layer 24, e.g. WSi_(x). Insulativematerial 26 is provided over the conductive lines and preferably coverslayers 22, 24. In the illustrated example, insulative material 26comprises a first insulative material 28 and a second insulativematerial 30 which is different from first insulative material 28.Preferably, the first and second insulative materials are selected suchthat one can be etched selectively relative to the other.

In this example, first insulative material 28 comprises an oxidematerial and second insulative material 30 comprises a nitride material.The first insulative material 28 can be formed to a thickness of around80 Angstroms over the sidewalls of each conductive line, and to around300 Angstroms over top portions of the conductive lines. A suitableoxide material for first insulative material 28 is an oxide formedthrough decomposition of TEOS. Second insulative material 30 can beformed to a thickness over the top portions of conductive lines 18, 20of around 1900 Angstroms (not shown to scale). An exemplary material forsecond insulative material 30 is silicon nitride. Of course, othermaterials, including other oxide and nitride materials are possible formaterials 28, 30.

Referring to FIG. 2, a photomasking layer 32 is formed over substrate 12and conductive lines 18, 20. Masking layer 32 has been patterned to formmasking layer openings 34, 36 which are received over conductive lines18, 20, respectively. The openings are preferably contemporaneouslyformed. In the illustrated example, opening 34 has a different, largertransverse cross-sectional dimension than opening 36. Opening 34 isdimensioned such that insulative material 26 over conductive line 18 isentirely exposed therethrough, while insulative material 26 overconductive line 20 is only partially exposed through opening 36. Opening34 is preferably formed over a substrate area where doping impuritiesare primarily intended to be provided, while opening 36 is formed over asubstrate area where etching is primarily intended to take place.Preferably, the etching which is to take place through opening 36 formsa contact opening to conductive line 20, as will become apparent below.

Referring to FIGS. 2 and 5, a preferred embodiment is set forth. There,memory circuitry, such as dynamic random access memory (DRAM) circuitry,is being formed over substrate 12. Accordingly, conductive lines 38 areformed over a memory array area of substrate 12, and other conductivelines 18, 20, are formed over a substrate area comprising a peripheralarea proximate the memory array. In the photomasking step justdescribed, the memory array is entirely masked with masking layer 32,and remains so masked during the processing which is described justbelow. Accordingly, such constitutes keeping the memory array maskedwith masking layer 32 while forming openings, i.e., openings 34, 36,over the peripheral area.

Referring to FIG. 3, doping impurities are provided into substrate 12proximate conductive line 18 sufficient to form diffusion regions 40.Doping of the substrate preferably comprises providing n+ dopant to formthe diffusion regions. Some doping impurities can be received throughopening 36 and into insulative material 30, but do not meaningfullyaffect conductive line 20.

Referring to FIGS. 3 and 4, doping impurities are provided into thesubstrate through openings 34, 36, and material of the substrate isetched through the openings. In a preferred embodiment, the doping ofthe substrate takes place prior to, and in a separate step from, theetching of the substrate material. In the illustrated example, theopenings are dimensioned to permit some of the doping impurity to bereceived by the substrate as diffusion regions through only some of theopenings. Accordingly, diffusion regions 40 are formed only relative toopening 34 and not opening 36. Of course, doping can take place afterthe etching of the substrate material through the openings.

Referring to FIG. 4, material of the substrate is etched through all ofthe openings, e.g., openings 34, 36. Such constitutes removing materialfrom over the conductive lines and, in particular, from over conductiveline 20 wherein a contact opening is at least partially formed thereto.Preferably, second insulative material 30 is dry etched selectivelyrelative to first insulative material 28. Exemplary etching conditionsinclude, in the context of a Lam 9400 etcher, a pressure of 20 mTorr,500 Watts source power, 0 Watts bias power, 40 sccm SF₆, and 20 sccmHBr. Such etch conditions can etch nitride at a rate of about 1200Angstrom/minute and oxide at a rate of about 100 Angstrom/minute. Suchetching can take place either anisotropically or isotropically. In theillustrated example, the etching of the second layer comprises anisotropic etch which removes insulative material from the sides of bothconductive lines.

The inventive methods can reduce processing complexity by combining, ina single masking step, the doping of impurities into a substrate throughopenings formed in a mask layer and the etching of material of thesubstrate through the openings. In a preferred embodiment, the methodsare employed in the formation of memory circuitry, and in particularDRAM circuitry. Accordingly, and in the preferred embodiment, processingcan now take place to form capacitor constructions over the memory array(FIG. 5).

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method comprising, in a single maskingstep, doping impurities into a substrate through openings formed in amask layer, and etching material of the substrate through said openings.2. The semiconductor processing method of claim 1 further comprisingdoping the impurities into the substrate prior to etching the substratematerial.
 3. The semiconductor processing method of claim 1, whereinsome of the openings have different transverse cross-sectionaldimensions than other of the openings.
 4. The semiconductor processingmethod of claim 1, wherein the substrate comprises a bulkmonocrystalline substrate and the openings are dimensioned to permitsome of the impurity to be received by the substrate as diffusionregions only through some of the openings.
 5. The semiconductorprocessing method of claim 1, wherein two openings are received overindividual conductive lines which are covered with insulative material,and the etching of the substrate material comprises etching portions ofthe insulative material.
 6. The semiconductor processing method of claim5, wherein the etching comprises isotropically etching said insulativematerial.
 7. The semiconductor processing method of claim 5, wherein theetching comprises anisotropically etching said insulative material. 8.The semiconductor processing method of claim 5, wherein the insulativematerial comprises first and second different insulative material, andthe etching comprises selectively etching one relative to the other. 9.The semiconductor processing method of claim 8, wherein the oneinsulative material comprises a nitride material.
 10. A semiconductorprocessing method of forming integrated circuitry comprising: forming aphotomasking layer over a substrate; contemporaneously forming openingsin the photomasking layer over substrate areas where impurities are tobe provided, and other substrate areas where etching is to take place;and in separate steps, doping the substrate with impurities through saidopenings and etching the substrate through said openings.
 11. Thesemiconductor processing method of claim 10 further comprising dopingthe substrate prior to etching the substrate.
 12. The semiconductorprocessing method of claim 10, wherein one opening is formed over aconductive line, and further comprising providing impurities into thesubstrate proximate the conductive line.
 13. The semiconductorprocessing method of claim 10, wherein the substrate comprises a *bulksubstrate, and further comprising providing impurities through theopenings, the openings being dimensioned to permit formation ofdiffusion regions within the bulk substrate proximate only some of theopenings.
 14. The semiconductor processing method of claim 10 furthercomprising etching substrate material through all of the openings. 15.The semiconductor processing method of claim 10, wherein the forming ofthe openings comprises forming two spaced-apart openings over first andsecond different insulative materials, and further comprisingselectively etching one of the insulative materials within the openingsrelative to the other of the insulative materials within the openings.16. The semiconductor processing method of claim 15, wherein the etchingcomprises isotropically etching said material.
 17. The semiconductorprocessing method of claim 15, wherein the etching comprisesanisotropically etching said material.
 18. A semiconductor processingmethod of forming integrated circuitry comprising: forming twoconductive lines over a substrate; forming a masking layer over the twoconductive lines; forming two openings through the masking layer in thesame step, one of the openings being received over one conductive line,another of the openings being received over the other conductive line;providing impurity through the one opening and into the substrateproximate the one conductive line; and removing material over the otherconductive line through the other opening to at least partially form acontact opening over the other conductive line.
 19. The semiconductorprocessing method of claim 18, wherein the forming of the two openingscomprises forming the one opening to have a larger transversecross-section than the other of the openings.
 20. The semiconductorprocessing method of claim 18, wherein the removing comprises removingmaterial from over both conductive lines.
 21. The semiconductorprocessing method of claim 18, wherein the other conductive linecomprises insulative material disposed over a top portion of theconductive line, the insulative material comprising first and seconddifferent insulative materials, and wherein the removing comprisesselectively etching one of the insulative materials relative to theother of the insulative material.
 22. The semiconductor processingmethod of claim 21, wherein the one insulative material comprises anitride material.
 23. The semiconductor processing method of claim 18,wherein both conductive lines comprise insulative material disposed overrespective top portions thereof, the insulative material comprisingfirst and second different insulative materials, and wherein theremoving comprises selectively etching one of the insulative materialsrelative to the other of the insulative material.
 24. A semiconductorprocessing method of forming integrated circuitry comprising: formingtwo conductive lines over a substrate, the lines comprising first andsecond insulative materials which are different from one another;forming a masking layer over the two conductive lines; forming twoopenings through the masking layer, one of the openings being receivedover one of the conductive lines, another of the openings being receivedover the other conductive line; providing impurity through the oneopening and into the substrate proximate the one conductive line; andetching one of the first and second insulative materials to at leastpartially form a contact opening to at least one of the conductivelines.
 25. The semiconductor processing method of claim 24 furthercomprising providing the impurity into the substrate prior to theetching of the one insulative material.
 26. The semiconductor processingmethod of claim 24 further comprising etching the one of the first andsecond insulative materials prior to the providing of the impurity. 27.The semiconductor processing method of claim 24, wherein the etching ofthe one of the first and second insulative materials comprisingselectively etching said one material relative to the other of the firstand second insulative materials.
 28. The semiconductor processing methodof claim 24, wherein the forming of the two openings comprises formingsaid openings to have different transverse cross sections.
 29. Thesemiconductor processing method of claim 24, wherein insulative materialof only one conductive line is entirely exposed through an opening. 30.The semiconductor processing method of claim 24, wherein the oneinsulative material comprises a nitride material.
 31. A semiconductorprocessing method of forming DRAM circuitry comprising: forming aplurality of conductive lines over a substrate, some of the conductivelines being formed over a memory array area of the substrate, otherconductive lines being formed over a substrate area comprising aperipheral area proximate the memory array; forming a masking layer overthe substrate; in the same masking step, forming a plurality of openingsthrough the masking layer over the peripheral area while keeping thememory array masked with the masking layer; providing impurity throughthe openings; and removing material from over the conductive linesthrough the openings.
 32. The semiconductor processing method of claim31 further comprising providing the impurity prior to removing thematerial from over the conductive lines.